The present invention relates to the measurement of semiconductor wafer characteristics and, more particularly, to the deposition of a desired charge upon the surface of such a wafer.
In order to perform various tests to characterize the electrical parameters and quality of semiconductor wafers, it is desirable to be able to produce uniform charge densities on the surface of the wafer.
For example, it is common to rinse a wafer in water to remove any charge that has accumulated on the oxide layer formed on the surface of the wafer.
Such a rinsing entails not only the rinsing step, but also, a drying step. This increases the chances for contamination and damage of the wafer. In addition, the drying process may reintroduce charge gradients.
U.S. Pat. No. 5,594,247, discloses an apparatus and method for depositing corona charge on a wafer and is incorporated herein by reference. A conductive grid is placed between a corona charge source and the wafer. A potential applied to the grid is used to control the amount of charge applied to the wafer. The invention disclosed in the patent provides excellent uniform charge deposition for wafers having thick oxide layers (e.g., greater than 150 Angstroms). However, as the oxide layer becomes thinner, the permissible voltage across the layer becomes smaller (e.g., 1 volt). As a result, second order effects that could previously be ignored need to be dealt with. In particular, work function variations (e.g., 10 to 100 millivolts) on the grid may create unacceptable variations in the deposited charge density. Areas, for example, less than 0.05 millimeters in diameter may have, for example, microgradients of 5E9 charges per centimeter squared per millimeter. Such a gradient would limit the lowest measurable interface state density to about 1.5E10 charges per centimeter squared per election volt at midgap.
These microgradients cause errors, for example, in the measurement of interface states charge densities in the wafer. In addition, microgradients cause further errors as smaller areas of a wafer are examined.